The semiconductor industry continually strives to increase device performance and device density by reducing device dimensions. More specifically, in the past the area on a chip occupied by active devices, known as the active area, and area on a chip used to isolate active devices, known as the isolation area, have been reduced in order to achieve higher device packing densities and improved device performance. This continuing reduction in device dimensions, however, has also begun to adversely effect the performance and the reliability of these scaled devices. This is because device parasitics, such as contact resistance, begin to limit the performance and reliability of these devices as they are scaled.
One technique which has been proposed for reducing the area required to isolate active devices in high density integrated circuits is trench isolation. With trench isolation, field oxide encroachment into the surrounding active area is eliminated, and therefore the area required for both device isolation and active devices can be simultaneously reduced. Unfortunately, reducing the active area of a device also reduces the area available to make contact to that device. As a result, devices having submicron design rules have small contact areas, and therefore the parasitic resistance associated with contacting these submicron devices can be high because contact resistance is dependent on contact area. Moreover, at submicron dimensions the parasitic resistance associated with these small contacts becomes high enough to limit the speed at which integrated circuits perform and to degrade device reliability. Accordingly, a need exists for a contact structure that allows high density integrated circuits to be fabricated with low contact resistance.